1. Field of the Invention
This invention relates to optical transceivers. In particular, this invention relates to an optical transceiver and input buffer therefor, especially suitable for use in infrared transceiver systems.
2. Background of the Invention
An optical receiver converts optical pulses to corresponding electrical signals. For example, the optical receiver in an infrared (IR) optical transceiver commonly used for wireless data transfer typically utilizes an IR-sensitive diode which emits an electric current in proportion to the intensity of infrared light striking the active area of the diode. An optical transmitter of an optical transceiver sends out optical pulses according to the input electrical signal applied on the input buffer.
The input buffer of an IR transceiver is an inverter which has certain desirable characteristics:
1. Hysteresis: Hysteresis is necessary to improve the system noise immunity and input signal stability. Ideally an IR transceiver input buffer input-output characteristics should exhibit symmetrical hysteresis, wherein the up-threshold and down-threshold are symmetrical about the pulse width definition point, usually taken as one half of the power supply voltage. This is especially important to the input of the transceiver, which should maintain the output pulse width the same as the input pulse.
2. Zero static current: Zero static current for both logic high and logic low states is highly desirable. It is required in certain situations, for example by the active high input signal of SD (shut down) mode, because when an IR transceiver is in shut down mode the transceiver power current can be as low as 50 nanoamperes, and thus an input buffer current on the order of microamperes is unacceptable and unworkable.
3. Multi-channel: The buffer should have the capability of interfacing with different input signal modes such as TTL, 5V CMOS, 3.3V CMOS, 2.7V CMOS and so on, each of which has a different voltage swing and thus requires a different threshold voltage.
4. Automatic pull down: When a mechanical switch is connected to the input buffer the input pin may be floating electrically, which would cause uncertainty in the logic status. The input buffer should have the capability of detecting the floating condition during power on reset and automatically pull down the input to a logic low status.
There are two conventional prior art input buffers. FIG. 1 shows a CMOS inverter, which has zero static current but has no hysteresis. FIG. 2 shows a source coupling input buffer, which has hysteresis but its static current is not zero because one of the FETs U1 or U2 is always turned on.
The present invention addresses these problems by providing an input buffer circuit for an optical transceiver which provides symmetrical hysteresis and zero static current. The input buffer comprises two field effect transistors (FETs) which form the basic buffer logic circuit, two FETs which respectively provide offset voltages to the buffer logic FETs, and two FETs which provide positive feedback.
In the preferred embodiment the input buffer of the invention is programmable, providing multiple-channels, each channel comprising a component inverter designed to provide zero static current and symmetrical hysteresis for a different input signal mode. The multi-channel input buffer of the invention, which can be embodied in a single microchip, can thus accommodate input signals having different characteristics without sacrificing the symmetrical hysteresis of the output signal.
The present invention thus provides a multiple-channel input buffer circuit, comprising a pair of logic transistors comprising a p-type transistor coupled in series, drain to drain, with an n-type transistor, a pair of voltage offset transistors comprising a p-type transistor having a drain coupled to a source of the p-type logic transistor and a source coupled to a power supply and an n-type transistor having a drain coupled to a source of the n-type logic transistor and a source coupled to ground, an input terminal coupled to gates of the logic and voltage offset transistors, and a plurality of pairs of feedback transistors, each pair of feedback transistors comprising a p-type transistor having a source coupled to a junction of the p-type logic and voltage offset transistors, a gate coupled to an output terminal and a drain coupled to ground through a switching circuit and an n-type transistor having a source coupled to a junction of the n-type logic and voltage offset transistors, a gate coupled to the output terminal and a drain coupled to a voltage supply through the switching circuit, wherein when the switching circuit associated with a pair of feedback transistors is activated, the feedback transistors supply a positive feedback to control a conductivity of the logic transistors and vary a voltage level on the output terminal.
The present invention further provides an optical transceiver having an input buffer circuit, the input buffer circuit comprising a pair of logic transistors comprising a p-type transistor coupled in series, drain to drain, with an n-type transistor, a pair of voltage offset transistors comprising a p-type transistor having a drain coupled to a source of the p-type logic transistor and a source coupled to a power supply and an n-type transistor having a drain coupled to a source of the n-type logic transistor and a source coupled to ground, an input terminal coupled to gates of the logic and voltage offset transistors, and a plurality of pairs of feedback transistors, each pair of feedback transistors comprising a p-type transistor having a source coupled to a junction of the p-type logic and voltage offset transistors, a gate coupled to an output terminal and a drain coupled to ground through a switching circuit and an n-type transistor having a source coupled to a junction of the n-type logic and voltage offset transistors, a gate coupled to the output terminal and a drain coupled to a voltage supply through the switching circuit, wherein when the switching circuit associated with a pair of feedback transistors is activated, the feedback transistors supply a positive feedback to control a conductivity of the logic transistors and vary a voltage level on the output terminal.
In further aspects of the multiple-channel input buffer circuit and the optical transceiver of the invention: the input terminal is coupled to a pull down circuit; the pull down circuit comprises a resistance path to ground through a switch and a resistor, and an inverter having an inverter input coupled to the input terminal and an inverter output coupled to the switch, wherein when the input is low or floating the inverter output renders the switch conductive to close the path to ground to ground the input through the resistor; the pull down circuit comprises a second resistance path to ground through a second switch, the second switch being rendered conductive by a power on reset signal; each switching circuit comprises a switching terminal connected to an n-type transistor and connected through an inverter to a p-type transistor, whereby a high logic signal applied to the switching terminal closes respective paths between the feedback transistors and power terminals supplying power to the circuit; and/or the transistors are field effect transistors.
The present invention further provides an input buffer circuit comprising a pair of logic transistors comprising a p-type transistor coupled in series, drain to drain, with an n-type transistor, a pair of voltage offset transistors comprising a p-type transistor having a drain coupled to a source of the p-type logic transistor and a source coupled to a power supply and an n-type transistor having a drain coupled to a source of the n-type logic transistor and a source coupled to ground, an input terminal coupled to gates of the logic and voltage offset transistors, and a pair of feedback transistors comprising a p-type transistor having a source coupled to a junction of the p-type logic and voltage offset transistors, a gate coupled to an output terminal and a drain coupled to ground and an n-type transistor having a source coupled to a junction of the n-type logic and voltage offset transistors, a gate coupled to the output terminal and a drain coupled to a voltage supply, wherein the feedback transistors are respectively selected according to the formulae:
Idsp=Gp*[(Va+Vthp)2]*Wp/(2*Lp)
and
Idsn=Gn*[(VDDxe2x88x92Vbxe2x88x92Vthn)2]*Wn/(2*Ln)
where:
Idsp=the drain-to-source current of the p-type feedback transistor,
Vthp=threshold voltage of the p-type feedback transistor,
Wp=channel width of the p-type feedback transistor,
Lp=channel length of the p-type feedback transistor,
Va=the voltage at the source of the p-type feedback transistor,
Gp=the transconductance of the p-type feedback transistor,
Idsn=the drain-to-source current of the n-type feedback transistor,
Vthn=threshold voltage of the n-type feedback transistor,
Wn=channel width of the n-type feedback transistor,
Ln=channel length of the n-type feedback transistor,
Vb=the voltage at the source of the n-type feedback transistor, and
Gn=the transconductance of the n-type feedback transistor,
to independently determine an up threshold and a down threshold of the input buffer circuit and thereby to provide an output signal having symmetrical hysteresis.
In further aspects of the input buffer circuit of the invention: the pull down circuit comprises a resistance path to ground through a switch and a resistor, and an inverter having an inverter input coupled to the input terminal and an inverter output coupled to the switch, wherein when the input is low or floating the inverter output renders the switch conductive to close the path to ground to ground the input through the resistor; the pull down circuit comprises a second resistance path to ground through a second switch, the second switch being rendered conductive by a power on reset signal; the transistors are field effect transistors; the circuit comprises a plurality of pairs of feedback transistors, each p-type feedback transistor having a drain coupled to ground through a switching circuit and each n-type feedback transistor having a drain coupled to the power supply through the switching circuit, wherein when the switching circuit associated with a pair of feedback transistors is activated the feedback transistors supply a positive feedback to control a conductivity of the logic transistors and vary a voltage level on the output terminal; and/or each switching circuit comprises a switching terminal connected to an n-type transistor and connected through an inverter to a p-type transistor, whereby a high logic signal applied to the switching terminal closes respective paths between the feedback transistors and power terminals supplying power to the circuit.